How to include clean target in Makefile?
The best thing is probably to create a variable that holds your binaries:
binaries=code1 code2Then use that in the all-target, to avoid repeating:
all: clean $(binaries)Now, you can use this with the clean-target, too, and just add some globs to catch object files and stuff:
.PHONY: cleanclean: rm -f $(binaries) *.oNote use of the .PHONY to make clean a pseudo-target. This is a GNU make feature, so if you need to be portable to other make implementations, don't use it.
By the way it is written, clean rule is invoked only if it is explicitly called:
make clean
I think it is better, than make clean every time. If you want to do this by your way, try this:
CXX = g++ -O2 -Wallall: clean code1 code2code1: code1.cc utilities.cc $(CXX) $^ -o $@code2: code2.cc utilities.cc $(CXX) $^ -o $@clean: rm ... echo Clean done